Jan. 1st, 2010 02:08 am
Here's to a better 2010!
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joshua01)
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2)
This indicates that the layout passes tests. That is post-Assura extraction, which means that it includes parasitic capacitance. All that remains for me to do now is delay measurements, and I'm home free!
(click for more, and bigger).
2)
joshua@escape:~$ linux grep Check simulation/TopLevelTB/UltraSim/schematic/psf/input.veclog ****VectorCheck for out_bus_15: All good! ****VectorCheck for out_bus_14: All good! ****VectorCheck for out_bus_13: All good! ****VectorCheck for out_bus_12: All good! ****VectorCheck for out_bus_11: All good! ****VectorCheck for out_bus_10: All good! ****VectorCheck for out_bus_9: All good! ****VectorCheck for out_bus_8: All good! ****VectorCheck for out_bus_7: All good! ****VectorCheck for out_bus_6: All good! ****VectorCheck for out_bus_5: All good! ****VectorCheck for out_bus_4: All good! ****VectorCheck for out_bus_3: All good! ****VectorCheck for out_bus_2: All good! ****VectorCheck for out_bus_1: All good! ****VectorCheck for out_bus_0: All good! joshua@escape:~$
This indicates that the layout passes tests. That is post-Assura extraction, which means that it includes parasitic capacitance. All that remains for me to do now is delay measurements, and I'm home free!